Time Day 1 (Dec. 11) Time Day 2 (Dec. 12) Time Day 3 (Dec. 13) Time Day 4 (Dec. 14)
09:00~09:20 Opening 09:00~10:20 Application and Security 08:40~09:40 High-Level Design
09:20~10:40 Best Paper Candidates and Journal Track Paper 10:40~12:00 Machine Learning 2 10:00~11:00 Arithmetic
11:00~12:00 Machine Learning 1 11:20~12:20 Invited Talk 2
12:20~12:30 Closing and Award Ceremony
13:30-17:00 Tutorial 1 by AMD 13:30~14:30 Keynote 13:30~14:50 Poster Session 14:00~15:30 Tutorial 2 by Intel
14:50~16:30 Design Technology 15:00~16:40 Memory System and Architecture
16:40~17:40 Demo Night Ph.D. Forum 17:00~18:00 Invited Talk 1
18:30~20:30 Welcome Reception 19:00~21:00 Banquet

Day 1 (Dec. 11) PM

13:30~17:00, Tutorial 1

Day 2 (Dec. 12) AM

08:00, Registration Open

09:00~09:20, Opening

  • Hiroki Nakahara (Tohoku University, Japan)
  • Shinya Takamaeda-Yamazaki (The University of Tokyo, Japan)

09:20~10:40, Session 1: Best Paper Candidates and Journal Track Paper

Session Chair: Shinya Takamaeda (The University of Tokyo, Japan)

  • Marta Andronic and George A. Constantinides (Imperial College London, UK), “PolyLUT: Learning Piecewise Polynomials for Ultra-Low Latency FPGA LUT-based Inference”, Best Paper Candidate, Artifact: Available, Reviewed, Reproducible
  • Andrew Boutros, Fatemehsadat Mahmoudi, Amin Mohaghegh, Stephen More, and Vaughn Betz (University of Toronto, Canada), “Into the Third Dimension: Architecture Exploration Tools for 3D Reconfigurable Acceleration Devices”, Best Paper Candidate, Artifact: Available
  • Nils Albartus, Maik Ender, Jan-Nikals Möller, Marc Fyrbiak, Christof Paar (Max Planck Institute for Security and Privacy, Germany), and Russell Tessier (University of Massachusetts Amherst, USA), "On the Malicious Potential of Xilinx’ Internal Configuration Access Port (ICAP)" (Journal Track)
  • Theodoros Trochatos, Anthony Etim, and Jakub Szefer (Yale University, USA), "Covert-channels in FPGA-enabled SmartSSDs" (Journal Track)

11:00~12:00, Session 2: Machine Learning 1

Session Chair: Hayden So (University of Hong Kong, Hong Kong)

  • Geng Yang, Jie Lei (Xidian University, China), Zhenman Fang (Simon Fraser University, Canada), Yunsong Li, Jiaqing Zhang, and Weiying Xie (Xidian University, China), "HyBNN: Quantifying and Optimizing Hardware Efficiency of Binary Neural Networks" (Journal Track)
  • Mohamed Ibrahim (University of Toronto, Canada), Zhipeng Zhao (Carnegie Mellon University, USA), Mathew Hall (Microsoft, USA), and Vaughn Betz (University of Toronto, Canada), "Extending Data Flow Architectures for Convolutional Neural Networks to Multiple FPGAs"
  • Qi Liu, Mo Sun, Jie Sun, Liqiang Lu (Zhejiang University, China), Jieru Zhao (Shanghai Jiao Tong University, China), and Zeke Wang (Zhejiang University, China), "SSiMD: Supporting Six Signed Multiplications in a DSP Block for Low-Precision CNN on FPGAs"

Day 2 (Dec. 12) PM

13:30~14:30, Keynote

Session Chair: Hiroki Nakahara (Tohoku University, Japan)

    Speaker: Masato Motomura (Tokyo Institute of Technology, Japan)
    Title: The Future of Low-bitwidth Reconfigurable and Parallel AI Computing

    Abstract: Today’s AI computing systems must handle both the explosions of input data and output solutions. Toward a greener and smarter society in the near future, those explosions must be processed with as low energy as possible while keeping the versatility of the information systems. Hence reconfigurable, low-bitwidth, and massively parallel computing architectures are getting more critical as they represent the best strategy to reduce both the memory usage and computation energy at once for a variety of applications. The talk will examine algorithm-level, architecture-level, and real-chip-level topics explored in the design efforts belonging to that architectural category. Hardware-software co-optimization examples embedded in these design showcases will be a key takeaway of the talk.

    Bio: Masato Motomura graduated and also received Ph.D. from Kyoto University. He was a researcher at NEC central research labs, then became a professor at Hokkaido University. Now he is at the Tokyo Institute of Technology, leading the AI computing research unit. He is actively working on reconfigurable and parallel architectures for deep neural networks, machine learning, annealing machines, and intelligent computing in general. He has been awarded IEEE JSSC Annual Best Paper Award, the IPSJ Annual Best Paper Award, the IEICE Achievement Award, IEEE Fellow, Ichimura Award, and Yamasaki Award.

14:50~16:30, Session 3: Design Technology

Session Chair: Kota Ando (Hokkaido University, Japan)

  • Emanuele Del Sozzo (RIKEN Center for Computational Science, Japan), Davide Conficconi (Politecnico di Milano, Italy), and Kentaro Sano (RIKEN Center for Computational Science, Japan), "Across Time and Space: Senju's Approach for Scaling Iterative Stencil Loop Accelerators on Single and Multiple FPGAs" (Journal Track)
  • Fatemehsadat Mahmoudi, Mohamed A. Elgammal, Soheil Gholami Shahrouz (University of Toronto, Canada), Kevin E. Murray (Cerebras Systems, Canada), and Vaughn Betz (University of Toronto, Canada), "Respect the Difference: Reinforcement Learning for Heterogeneous FPGA Placement"
  • Timothy Martin, Qi Li, Charlotte Barnes, Gary Grewal, and Shawki Areibi (University of Guelph, Canada), "A Deep-Learning Data-Driven Approach for Reducing FPGA Routing Runtimes"
  • Maximillian Kealoha Panoff, Muhammed Kawser Ahmed, Hanqiu Wang, Shuo Wang, and Christophe Bobda (University of Florida, USA), "A Tenant Side Compilation Solution for Cloud FPGA Deployment"
  • Reilly McKendrick, Keenan Faulkner, and Jeffrey Goeders (Brigham Young University, USA), "Assuring Netlist-to-Bitstream Equivalence using Physical Netlist Generation and Structural Comparison", Artifact: Available

16:40~17:40, Demo Night Ph.D. Forum

Demo Night

  • Kanta Yoshioka, Yuichiro Tanaka, and Hakaru Tamukoh (Kyushu Institute of Technology, Japan), "Traffic Flow Optimization using a Chaotic Boltzmann Machine Annealer on an FPGA"
  • Akinobu Tomori and Yasunori Osana (Kumamoto University, Japan), "Kyokko: a Virtual channel capable Aurora 64B/66B compatible Serial Communication Controller"
  • Hayato Mori (Shibaura Institute of Technology, Japan), Eisuke Okazaki, Gai Nagahashi, Mikiko Sato (Tokai University, Japan), Takeshi Ohkawa (Kumamoto University, Japan), and Midori Sugaya (Shibaura Institute of Technology, Japan), "Offloading Image Recognition Processing for Care Robots to FPGA on Multi-access Edge Computing"
  • Kaijie Wei (Keio University, Japan), Ryohei Niwase (University of Tsukuba, Japan), Hideharu Amano (Keio University, Japan), Yoshiki Yamaguchi (University of Tsukuba, Japan), and Takefumi Miyoshi (WasaLabo, LLC., Japan), "A state vector quantum simulator working on FPGAs with extensible SATA storage"
  • Taiga Kubuta, Duckgyu Shin, Naoya Onizawa, and Takahiro Hanyu (Tohoku University, Japan), "Stochastic Implementation of Simulated Quantum Annealing on PYNQ"

Ph.D. Forum

  • Kaichuang Shi, Hao Zhou, and Lingli Wang (Fudan University, China), "Explore the Feedback Interconnects in Intra-Cluster Routing for FPGAs"
  • Tingting Qiao, Yu Xie, He Chen, and Yizhuang Xie (Beijing Institute of Technology, China), "An FPGA-GPU Heterogeneous System and Implementation for On-Board Remote Sensing Data Processing"
  • Ning Zhang, Shuo Ni, Tingting Qiao, Wenchao Liu, and He Chen (Beijing Institute of Technology, China), "An Extremely Pipelined FPGA-based accelerator of All Adder Neural Networks for On-board Remote Sensing Scene Classification"
  • Ryota Miyagi (The University of Tokyo, Japan), Ryota Yasudo (Kyoto University, Japan), Kentaro Sano (RIKEN, Japan), and Hideki Takase (The University of Tokyo, Japan), "Performance Modeling and Scalability Analysis of Stream Computing in ESSPER FPGA clusters"

18:30~20:30 - Welcome Reception

Day 3 (Dec. 13) AM

08:00 - Registration Open

09:00~10:20, Session 4: Application and Security

Session Chair: Jiafeng Xie (Villanova University, USA)

  • Timo Haarman, Antonio Almeida, Amber Heskes, Floris Zwanenburg, and Nikolaos Alachiotis (University of Twente, Netherlands), "FPGA-accelerated Quantum Transport Measurements"
  • Xiaobei Yan, Xiaoxuan Lou, Guowen Xu (Nanyang Technological University, Singapore), Han Qiu (Tsinghua University, China), Shangwei Guo (Chongqing University, China), Chip Hong Chang, and Tianwei Zhang (Nanyang Technological University, Singapore), "Mercury: An Automated Remote Side-channel Attack to Nvidia Deep Learning Accelerator"
  • Kanta Yoshioka, Yuichiro Tanaka, and Hakaru Tamukoh (Kyushu Institute of Technology, Japan), "LUTNet-RC: Look-Up Tables Networks for Reservoir Computing on an FPGA"
  • Weihai Xu, Zheng Zhou (Southeast University, Nanjing, China), Jin Zhang (Purple Mountain Laboratories, Nanjing, China), Yiming Jiang, and Peng Yi (National Digital Switching Engineering & Technological Research Center, China), "OD-REM: On-Demand Regular Expression Matching on FPGAs for Efficient Deep Packet Inspection"

10:40~12:00, Session 5: Machine Learning 2

Session Chair: Vaughn Betz (University of Toronto, Canada)

  • Zibo Guo, Kai Liu (Xidian University, China), Wei Liu (State Key Laboratory of Geo-information Engineering, China), and Shangrong Li (Xidian University, China), "Efficient FPGA-based Accelerator for Post-Processing in Object Detection"
  • Alexander Montgomerie-Corcoran, Petros Toupas, Zhewen Yu, and Christos-Savvas Bouganis (Imperial College London, UK), "SATAY: A Streaming Architecture Toolflow for Accelerating YOLO Models on FPGA Devices", Artifact: Artifact: Available, Reviewed, Reproducible
  • Zhengzheng Ma and Guojie Luo (Peking University, China), "An Efficient Dataflow for Convolutional Generative Models"
  • Frank Ridder, Kuan-Hsun Chen, and Nikolaos Alachiotis (University of Twente, Netherlands), "Accelerated Real-Time Classification of Evolving Data Streams using Adaptive Random Forests" (Short Paper)
  • Mo Song, Jiajun Wu, Yuhao Ding, and Hayden So (University of Hong Kong, Hong Kong), "SqueezeBlock: A Transparent Weight Compression Scheme for Deep Neural Networks" (Short Paper)

Day 3 (Dec. 13) PM

13:30~14:50, Poster Session

Please take a look at the instruction

  • Ryohei Niwase (University of Tsukuba, Japan), Kaijie Wei, Hideharu Amano (Keio University, Japan), Yoshiki Yamaguchi (University of Tsukuba, Japan), and Takefumi Miyoshi (WasaLabo, LLC., Japan), "Enormous-Scale Quantum State Vector Calculation with FPGA-accelerated SATA storages"
  • Yingchang Mao and Qiang Liu (Tianjin University, China), "MSTA: An FPGA-based Mix-grained Sparse Training Accelerator"
  • Benjamin Ramhorst, George A. Constantinides (Imperial College London, UK), and Vladimir Lončar (Massachusetts Institute of Technology, USA), "FPGA Resource-aware Structured Pruning for Real-Time Neural Networks"
  • Yuhang Cao, Yunhui Qiu, Xuchen Gao, Qilong Zhu, Wenbo Yin, and Lingli Wang (Fudan University, China), "E^2-ACE: An Energy-Efficient Reconfigurable Crypto-Accelerator with Agile End-to-End Toolchain"
  • Qilong Zhu, Yuhang Cao, Yunhui Qiu, Xuchen Gao, Wenbo Yin, and Lingli Wang (Fudan University, China), "A Dynamic Partial Reconfigurable CGRA Framework for Multi-Kernel Applications"
  • Liangji Chen, Tingyuan Liang, Wei Zhang (Hong Kong University of Science and Technology, Hong Kong), and Sharad Sinha (Indian Institute of Technology Goa, India), "DiffLo: A Graph-based Method for Functional Discrepancy Localization in High-level Synthesis"
  • Moucheng Yang, Kaixiang Zhu, and Lingli Wang (Fudan University, China), "DSLUT: An Asymmetric LUT and its Automatic Design Flow Based on Practical Functions from Domain-Specific Benchmarks"
  • Bizhao Shi, Jieran Zhang, and Guojie Luo (Peking University, China), "F-TFM: Accelerating Total Focusing Method for Ultrasonic Array Imaging on FPGA"
  • Zhenyu Wu, Mo Song, and Hayden So (University of Hong Kong, Hong Kong), "Towards Asynchronously Triggered Spiking Neural Network on FPGA for Event-based Vision"
  • Suquan Zhang, Jincheng Yu, Yuanfan Xu, and Yu Wang (Tsinghua University, China), "UAV Swarm Planning accelerator on FPGA with low latency and fixed-point L-BFGS Quasi-Newton solver"
  • Antonio Filgueras, Miquel Vidal, Daniel Jiménez-González, Carlos Álvarez, and Xavier Martorell (Universitat Politecnica de Catalunya, Spain), "FPGA framework improvements for HPC applications"
  • Edward Grindley, Thurstan Gray, James Wilkinson, Chris Vaux, Adam Ardron, Jack Deeley, Alexander Elliott (Alan Turing Institute, UK), Nidhin Thandassery Sumithran, and Suhaib A. Fahmy (University of Warwick, UK), "The NAIL Accelerator Interface Layer"
  • Zhen Li, and Lingli Wang (Fudan University, China), "Automated Efficient Approximate Multiplier Generator for FPGAs via Black-Box Optimization"
  • Sujan Kumar Saha, Abigail N. Butka, Muhammed Kawser Ahmed, and Christophe Bobda (University of Florida, USA), "OpenTitan based Multi-Level Security in FPGA System-on-Chips"

15:00~16:40, Session 6: Memory System and Architecture

Session Chair: Oliver Diessel (University of New South Wales, Australia)

  • [Online] Dongjoon Park, Zhijing Yao, Yuanlong Xiao, and André DeHon (University of Pennsylvania, USA), "Asymmetry in Butterfly Fat Tree FPGA NoC" (Short Paper)
  • Yuzong Chen, Jordan Dotzel, and Mohamed Abdelfattah (Cornell University, USA), "M4BRAM: Mixed-Precision Matrix-Matrix Multiplication in FPGA Block RAMs", Artifact: Reviewed, Reproducible
  • Robert Szafarczyk, Syed Waqar Nabi, and Wim Vanderbauwhede (University of Glasgow, UK), "A High-Frequency Load-Store Queue with Speculative Allocations for High-Level Synthesis", Artifact: Artifact: Available, Reviewed, Reproducible
  • Chia-Chen Yen (National Taiwan University, Taiwan), Mi-Yen Yeh (Academia Sinica, Taiwan), and Ming-Syan Chen (National Taiwan University, Taiwan), "Integrated Multi-Ported Memory Distribution for Temporal-Multiplexing Workloads on FPGAs"
  • Kaichuang Shi, Hao Zhou, and Lingli Wang (Fudan University, China), "VIB: A Versatile Interconnection Block for FPGA Routing Architecture"
  • Philippos Papaphilippou, Zhiqiang Que, and Wayne Luk (Imperial College London, UK), "Efficiently Removing Sparsity for High-Throughput Stream Processing" (Short Paper)

17:00~18:00, Invited Talk 1

Session Chair: Hideharu Amano (Keio University, Japan)

    Speaker: Shinpei Kato (Specially Appointed Professor, The University of Tokyo. Founder and CEO/CTO, TIER IV)
    Title: Autoware: The Art of Open Source Reimagines Intelligent Vehicles

    Abstract: As cars become ever more software-first, today's digital era creates unique opportunities while forcing auto manufacturers to rapidly evolve, and among increasingly complex automotive software developments, autonomous driving stands out from the crowd. The urgent need to develop software-defined vehicles (SDV), in which the value of a vehicle is dominated not by hardware but by software updates of functions and features, has become a major topic of discussion in the automotive industry. TIER IV has developed a full-stack open-source software for autonomous driving capabilities called Autoware together with a cloud-native DevOps environment, which is indispensable for the development of SDV and will soon be available also as an open-source package. In this session, TIER IV will explain why open source is critical in the development of autonomous driving capabilities and our strategy to penetrate this market.

    Bio: Shinpei is the founder and CEO / CTO of TIER IV, and a co-founder and chairman of the Autoware Foundation. He also works as a specially appointed professor for the Graduate School of Information Science and Technology at the University of Tokyo. An internationally renowned expert in computer science, and a pioneer in the evolution of open-source software for autonomous driving technology. Shinpei was an associate professor at the Graduate School of Information Science, Nagoya University, from 2012 to 2016, where his team created the world's first open-source software for autonomous driving technology, Autoware. He was also a postdoctoral scholar at Keio University, the University of Tokyo, Carnegie Mellon University, and University of California. His expertise includes computer architectures and operating systems for embedded and real-time systems as well as parallel and distributed systems.

19:00~21:00, Banquet

Day 4 (Dec. 14) AM

08:00 - Registration Open

08:40~09:40, Session 7: High-Level Design

Session Chair: Tomohiro Ueno (RIKEN R-CCS)

  • Jiangnan Li, Chang Cai (Fudan University, China), Yaya Zhao (Renmin University of China, China), Yazhou Yan, Wenbo Yin, and Lingli Wang (Fudan University, China), "GRAFT: GNN-based Adaptive Framework for Efficient CGRA Mapping"
  • Jingyuan Li, Yihan Hu, Yuan Dai, and Lingli Wang (Fudan University, China), "AUGER: A Multi-Objective Design Space Exploration Framework for CGRAs"
  • Huizhen Kuang, Xianfeng Cao, and Lingli Wang (Fudan University, China), "HGBO-DSE: Hierarchical GNN and Bayesian Optimization based HLS Design Space Exploration"

10:00~11:00, Session 8: Arithmetic

Session Chair: Jeffrey Goeders (Brigham Young University, USA)

  • Endri Taka (University of Texas at Austin, USA), Aman Arora (Arizona State University/University of Texas at Austin, USA), Kai-Chiang Wu (National Yang Ming Chiao Tung University, Taiwan, University of Texas at Austin, USA), and Diana Marculescu (University of Texas at Austin, USA), "MaxEVA: Maximizing the Efficiency of Matrix Multiplication on Versal AI Engine"
  • Baoze Zhao, Wenjin Huang, Tianrui Li, and Yihua Huang (Sun Yat-sen University, China), "BSTMSM: A High-Performance FPGA-based Multi-Scalar Multiplication Hardware Accelerator"
  • Tianyou Bao, Pengzhou He, Jiafeng Xie (Villanova University, USA), and H S. Jacinto (Air Force Research Lab Information Directorate, USA), "AEKA: FPGA Implementation of Area-Efficient Karatsuba Accelerator for Ring-Binary-LWE-based Lightweight PQC" (Journal Track)

11:20~12:20, Invited Talk 2

Session Chair: David Boland (The University of Sydney, Australia)

    Speaker: Brian C. Faith (CEO, QuickLogic Corporation)
    Title: Open-source FPGA development: A new era of innovation and growth

    Abstract: Radically changing a business model and R&D strategy is usually an undertaking by VC-backed startups, not 30+ year old companies. But this is exactly what QuickLogic has done. Our goal was to take the Programmable Logic market, consisting of proprietary, walled gardens and turn it on its head. In order to accomplish this, we needed to do what no other vendor in the history of the FPGA industry had done – embrace the free and open-source FPGA Tools community by providing architectural access to our FPGA devices and eFPGA IP cores. No need for reverse engineering. In late 2019, QuickLogic initiated a groundbreaking partnership with Google, enabling vendor-supported open-source FPGA development.
    But we didn't stop there. We set our sights on streamlining FPGA/eFPGA development, aiming to reduce it from 18 months to mere weeks, making FPGA chip design more like software development. Creating an FPGA with open-source tools presents a unique challenge, with the intricacies of FPGA design demanding significant time and resources, limiting widespread adoption. Enter the DARPA-funded project at the University of Utah – OpenFPGA. The goal of that project was to automate eFPGA IP creation from architectural descriptions, inching closer to the ambitious goal of “idea to GDSII netlist in 24 hours, no human in the loop”. Leveraging our 30+ years of experience in FPGAs and eFPGA IP cores, we're integrating our commercial best practices into this FPGA design automation. These new workflows now deliver 'commercial quality’ silicon at nearly software development speed, ushering a new era that empowers businesses to disrupt the FPGA and ASIC landscape.
    This presentation invites you to think big and seize the opportunity. The open sourcing of foundational tools, information, and specifications is imminent, potentially reshaping the industry within the next few years. Instead of fearing change, let's embrace it and explore the possibilities it offers for innovation and growth.

    Bio: Brian has 25+ years of experience in the FPGA industry, including 20+ years in a variety of leadership positions in Engineering, Product Line Management, Marketing, Sales, including 7 years as President and CEO. He is passionate about building business models that have open source foundations and making programmable logic available for the masses. Mr. Faith has also served as the board member of the Global Semiconductor Alliance (GSA), Founding Board Director of the Open-Source FPGA Foundation, and the Chairman of the Marketing Committee for the CE-ATA Organization. He holds a B.S. degree in Computer Engineering from Santa Clara University and was an Adjunct Lecturer at Santa Clara University for Programmable Logic courses.

12:20~12:30, Closing and Award Ceremony

  • Hiroki Nakahara (Tohoku University)
  • Shinya Takamaeda-Yamazaki (The University of Tokyo)

Day 4 (Dec. 14) PM

14:00~15:30, Tutorial 2

Presentation Instructions

Please read the following instructions and prepare your presentation.

For Oral Presentation

  • The location is 419 on the 4th floor of the Pacifico Yokohama Conference Tower.
  • The presentation is 20 minutes for regular/journal papers including 5 minutes Q&A.
  • The presentation is 10 minutes for short papers including 3 minutes Q&A.
  • Bring your own PC and HDMI connectors. Please greet the chairperson and check the connection before the start of the session.

For Poster Presentation

  • The location is 418 on the 4th floor of the Pacifico Yokohama Conference Tower (next to the presentation room).
  • The session is scheduled for 13:30-14:50 on 12/13 (Wed).
  • The organizing committee does not provide an official poster template.
  • Each presenter's poster must fit an A0-sized poster in portrait mode (33.1" x 46.8" or W841mm x H1189mm).
  • The size of the poster panel is W900mm x H2100mm. Posters are expected to be attached to the panel with studs.
  • Poster Booths can be set up from 08:00 on 12/13 (Wed) (when the booth opens). The booth area is designated as first come, first served.
  • No poster indexing. Please make a presentation at each poster booth once the session starts.
  • You may leave your poster panel attached after the poster session, but it must be removed by 17:30 on 12/13 (Wed). The venue will be locked at 19:00.

For Demo Night / Ph.D. Forum

  • The location is 418 on the 4th floor of the Pacifico Yokohama Conference Tower (next to the presentation room).
  • The session is scheduled for 16:40-17:40 on 12/12 (Tue).
  • Presentation Booths can be set up from 12:00 on 12/12(Tue). The booth area is designated as first come, first served.
  • Please move out of the booth promptly after the session. The venue will be locked at 19:00.
  • The rest of the instructions follow “For Poster Presentation”.